Design, analysis and experimental verification of an equalized 10Gbps link

Abstract

The demand for ever increasing data rates in digital systems must accommodate continuing demands for cost minimization. This leads to shrinking design margins that require precise analysis of the interactions and tradeoffs between different packaging options and equalization circuits required to compensate for channel impairments that result. This paper discusses the packaging design for demonstration 10Gbps links. Accurate measurements of the passive channels connecting the circuits verify EM simulations, and measurements of actual BER performance are correlated with link level simulations.