Data retention in SOI-DRAM with trench capacitor cell

Abstract

Data retention o/trench capacitor SOl-DRAM cells is investigated using 128Kbit fully functional test chip of 0.25 mu design rule. The data is compared with 128Khit bulk-Si DRAM made with the same design rule to clarify the loss mechanisms of data retention times for both SOl and bulk-Si. At 85°C, we found that data retention of SOl-DRAMs is iriferior to those of bulk-Si DRAMs. While bulk-Si DRAM retention fails are mainly due to cell transistor junction leakage to the substrate potential, SOl-DRAM fails are primarily due to cell transistor sub-the eshold leakage to the bit-line precharge potential. This is due to cell transistor floating body effects. To improve data retention times of SOl-DRAMs, we propose to lower the potential of the unselected word-lines below the used value of 0 Volts.