Control of sidewall roughness formation in through-silicon via etch at non-cryogenic temperatures

Abstract

Through-silicon via etch (TSV) is critical to current and future advanced packaging schemes. For heterogeneous integration approaches in particular, where modular components are tightly packed together, these processes play an integral role.1 While etch processes for silicon appear well understood and the frontiers of plasma etch have led us to advanced cyclic processes for device fabrication such as atomic layer etching, TSV applications are fundamentally different due to their relative size and aspect ratio targets. Unlike small-scale etching, TSV feature etching has not shown exponential change over time.2 To achieve TSV targets such as high etch rate, high aspect ratio, and clean profiles to support filling, known solutions are employed such as cryogenic wafer temperatures3, alternative hard mask schemes4, and extremely short gas cycle times 5; these solutions require specialized equipment and/or a more complex integration scheme. We explore the creation of high-aspect ratio, diffusion-limited TSV etches with high PR selectivity (>50:1) and high aspect ratios while simultaneously aiming for a high etch rate all while using non-cryogenic temperatures and a standard photoresist mask. A focus on sidewall profile and sidewall damage is maintained.