Comparative simulation study of InAs/Si and All-III-V hetero tunnel FETs

Abstract

Two different nanowire tunnel FETs, based either on the InAs/Si or the In0.53Ga0.47As/InP hetero-system, are investigated by device simulation. Variations of radius, equivalent oxide thickness, local doping, valence band offset, temperature, and the effect of trapassisted tunneling on the sub-threshold slope and the on-current of the transistors are demonstrated.