CMOS technology evolution: from 1 μm to 0.1 μm

Abstract

This paper reviews a number of key device and technology advances that enabled CMOS VLSI technology to evolve from 1 μm to 0.1 μm. They include: lithography, DRAM cell structure, shallow trench isolation, power supply voltage, thin gate oxide, n+/p+ polysilicon gate, shallow source-drain junctions, channel doping profile, and multilevel interconnect. Challenges to future scaling of CMOS technology are addressed at the end.