A 25Gb/s ADC-based serial line receiver in 32nm CMOS SOI
Sergey V. Rylov, Troy Beukema, et al.
ISSCC 2016
We have introduced a new class of dc-powered Single Flux Quantum (SFQ) logic that uses dynamic (self-resetting) internal states to achieve completely clock-free gate operation and provide high immunity to input data skew. We call it DSFQ (dynamic SFQ) logic. We have successfully designed and tested a 2-input DSFQ and gate and showed its ability to hold dynamically its internal states for over 25 ps while operating at 10 GHz clock frequency. We also demonstrated picosecond-scale dynamics of DSFQ circuit with an on-chip Josephson sampler, with only low-speed interfaces required.
Sergey V. Rylov, Troy Beukema, et al.
ISSCC 2016
Timothy O. Dickson, Yong Liu, et al.
IEEE Journal of Solid-State Circuits
Jonathan E. Proesel, Zeynep Toprak-Deniz, et al.
VLSI Circuits 2017
Jonathan E. Proesel, Zeynep Toprak-Deniz, et al.
IEEE JSSC