Circuit design challenges at the 14nm technology node

Abstract

Technology scaling non-idealities, already apparent in the transitions between previous technology generations, will become even more pronounced as the world moves from the 22nm node to the 14nm node. Digital logic designers working on high-performance microprocessors and similar projects will face significant new challenges as the basic FET structure is changed in a fundamental way, in order to squeeze more performance from scaled devices. New design constraints and new sources of variability will have to be understood, and new methodologies will be required to enable robust, high-speed designs. In addition, the metal interconnects between devices will also be stressed. Scaled wire RC will likely increase, and new tools and methods will be needed to ensure reliable designs. © 2011 ACM.