Circuit and PD challenges at the 14nm technology node

Abstract

As traditional CMOS scaling comes to an end, the industry is moving towards new 3D finFET multigate structures as device engineers stand the silicon transistors up on their sides. Digital circuit designers working in the 14nm technology node will face significant new challenges from additional design constraints and new sources of variability associated with this non-planar transistor structure. In addition, computational lithography and the need for double patterning at the 14nm node will drive up the complexity and difficulty of the physical design implementation, pushing designs towards more uniform and regular structures, even as wire RC and reliability issues drive increasing demand for uniquely customized solutions. New design tools and methodologies will therefore be needed to meet these circuit and PD challenges at the 14nm node. © 2013 ACM.