Miroslav Kotzev, Renato Rimolo-Donadio, et al.
IEEE Trans. Instrum. Meas.
Electrical loss and substrate noise coupling induced by through-silicon-vias (TSVs) in silicon-on-insulator (SOI) substrates is characterized in frequency and time domains. A three-dimensional (3-D) test site in 45-nm CMOS SOI including copper-filled TSVs and microbumps (μC4's) is fabricated and measured to extract the interconnect loss. Good correlation to the electrical circuit models is demonstrated up to 40 GHz. In addition to a buried oxide layer, a highly doped N+ epilayer used for deep trench devices in 22-nm CMOS SOI is considered in full-wave electromagnetic simulations. Equivalent circuit models are extracted to assess the impact of noise coupling on active circuit performance. A noise mitigation technique of using CMOS process compatible buried interface contacts is proposed and studied. Simulation results demonstrate that a low-impedance ground return path can be readily created for effective substrate noise reduction in 3-D IC design. © 2013 IEEE.
Miroslav Kotzev, Renato Rimolo-Donadio, et al.
IEEE Trans. Instrum. Meas.
Duixian Liu, Xiaoxiong Gu, et al.
APS 2015
Petar Pepeljugoski, Mark Ritter, et al.
SPIE IOPTO 2008
Mihai Telescu, Xiaoxiong Gu, et al.
IEEE Transactions on CPMT