Characterization and optimization of charge trapping in high-k dielectrics

Abstract

Continued scaling of semiconductor devices in logic and memory applications requires the introduction of high-k (HK) dielectrics to enhance the capacitance density while maintaining a low leakage. Of particular concern in DRAM memory applications is the so called 'dielectric relaxation current', which is significantly enhanced with HfO2 dielectrics as compared to SiO 2. In this paper, it is shown that these relaxation currents arise from electron trapping/detrapping by/from oxygen vacancy defects in the HfO 2 dielectric from/to the contact electrodes. This understanding is utilized to minimize 'dielectric relaxation currents' by optimizing the defect structure in the HK dielectric. By creating trap-free dielectric films with N or La doping, we show that substantial reductions in the relaxation currents can be achieved. For the first time, it is demonstrated that a HK dielectric stack formed as a result of these treatments can have reduced relaxation currents similar to SiO2, thus providing a pathway to solving a fundamental paradigm associated with HK dielectrics that has persisted for several years. © 2013 IEEE.