About cookies on this site Our websites require some cookies to function properly (required). In addition, other cookies may be used with your consent to analyze site usage, improve the user experience and for advertising. For more information, please review your options. By visiting our website, you agree to our processing of information as described in IBM’sprivacy statement. To provide a smooth navigation, your cookie preferences will be shared across the IBM web domains listed here.
Publication
IEDM 1983
Conference paper
CHARACTERIZATION AND MODELING OF A LATCHUP-FREE 1- mu M CMOS TECHNOLOGY.
Abstract
A 1- mu m CMOS technology using thin p/p** plus epi and shallow retrograde n-well is demonstrated to be latchup free since the holding voltage for latchup is higher than the 5-V power supply. Good agreement is obtained between the experimental result and simulations using a two-dimensional finite-element numerical analysis program. The sensitivity of latchup holding voltage to epi thickness and other structural parameters is also studied in the simulation.