Challenges in FEOL logic device integration for 32 nm technology node and beyond

Dae-Gyu Park; M. Chudzik; H. Yin

doi:10.1149/1.2778394

ECS Meeting 2007

Conference paper

07 Oct 2007

Challenges in FEOL logic device integration for 32 nm technology node and beyond

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Abstract

This paper provides a forum for reviewing and discussing new elements and challenges in the front end of line (FEOL) process integration for 32nm logic devices in the following areas: Metal/high-k (MHK) gate stack, mobility enhancement substrate technology with strain engineering. ©The Electrochemical Society.

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Abstract

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Resistivity of copper interconnects at 28 nm pitch and copper cross-sectional area below 100 nm2

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