Bipolar transistor scaling for minimum switching delay and energy dissipation

Abstract

A novel figure-of-merit to guide in the scaling of high-speed bipolar transistors is proposed. A method is described to relate the gate delay of a ring-oscillator to measurable device parameters analytically. The closed-form solution for an unloaded ECL (emitter coupled logic) gate agrees very well with published data of the past several years and with the results of circuit simulation. The formula for the basic current switch relates in a simple way the different device parameters and has been used to optimize device design for maximum speed and minimum energy dissipation.