Conference paper
SEAS: A System for Early Analysis of SoCs
Reinaldo A. Bergamaschi, Youngsoo Shin, et al.
CODES+ISSS 2003
Automating the design of system on a chip (SOC) using cores technique was presented. The cores or intellectual property (IP) blocks are used to quickly create SOC design with required complexity. The coreConnect architecture provides three buses namely processor local bus (PLB), on-chip peripheral bus (OPB) and device control-register (DCR) interconnects for interconnecting cores and custom logics. This technology brings a high-level abstraction to SOC design which enables easy reuse of existing components.
Reinaldo A. Bergamaschi, Youngsoo Shin, et al.
CODES+ISSS 2003
Nagu Dhanwada, Reinaldo A. Bergamaschi, et al.
Des Autom Embedded Syst
Reinaldo A. Bergamaschi, Salil Raje
IEEE Design and Test of Computers
Ruchir Puri, Leon Stok, et al.
DAC 2005