Reinaldo A. Bergamaschi, Salil Raje, et al.
IEEE Transactions on VLSI Systems
Automating the design of system on a chip (SOC) using cores technique was presented. The cores or intellectual property (IP) blocks are used to quickly create SOC design with required complexity. The coreConnect architecture provides three buses namely processor local bus (PLB), on-chip peripheral bus (OPB) and device control-register (DCR) interconnects for interconnecting cores and custom logics. This technology brings a high-level abstraction to SOC design which enables easy reuse of existing components.
Reinaldo A. Bergamaschi, Salil Raje, et al.
IEEE Transactions on VLSI Systems
Hiren D. Pate, Sandeep K. Shukla, et al.
DATE 2006
Martin Ohmacht, Reinaldo A. Bergamaschi, et al.
IBM J. Res. Dev
Daniel Brand, Reinaldo A. Bergamaschi, et al.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems