Architecture implications of 3D integration

Abstract

3D integration is a family of technologies for stacking silicon chips that exploit direct chip-to-chip interconnects and Through-Silicon-Vias (TSVs). 3D integration is currently being commercially exploited in memory and image sensor systems. Over time variations of this technology will work its way into more advanced uses in client and server systems. The exact roadmap for future exploitation is unclear, but some initial aspects are becoming known. The growth in the number of cores per chip in multicore designs is expected to keep increasing the total computational power per chip for the foreseeable future. This is putting tremendous stress on the cache and memory systems, and this more than anything else, will drive the need for 3D integration to implement larger caches in future client and servers systems. While implementing large caches will produce significant benefits in future multicore processors, the larger improvements will come later with designs that are optimized from the ground up to exploit dense 3D interconnections. The best way to do this is still unclear, but we will examine some of the possibilities as well as the major challenges for exploiting 3D integration in future server systems.