Analysis of the design space available for high-k gate dielectrics in nanoscale MOSFETs

Abstract

We present an analysis of the scaling behavior of MOSFETs with high-k gate insulators which elucidates the useful design space for such insulators. This analysis demonstrates that the design space is smaller than might be hoped and that within it, nanoscale bulk MOSFETs can only gain up to approx. 20% additional scaling by use of high-k insulators, while symmetric double-gated FETs may gain up to approx. 30%. It is shown that this analysis does not depend significantly on the gate sidewall dielectric constant or its spacing.