Conference paper
Extendibility of NiPt silicide to the 22-nm node CMOS technology
Kazuya Ohuchi, Christian Lavoie, et al.
IWJT 2008
Detailed analysis of a buried layer of GaAs in 〈100〉 Si was carried out using electron energy loss spectroscopy, Rutherford backscattering spectroscopy, and ion channeling. The layer was formed by 200 keV dual ion implantation of Ga plus As ions, followed by furnace annealing at 600 and 950°C. It consists of GaAs particles which are surrounded by fully recrystallized silicon. Beneath it is a dislocation network, made up of a mixture of edge and screw dislocations.
Kazuya Ohuchi, Christian Lavoie, et al.
IWJT 2008
Pouya Hashemi, Takashi Ando, et al.
VLSI Circuits 2015
Peter Madakson, Eti Ganin, et al.
Journal of Applied Physics
Martin Sandberg, Vivekananda P. Adiga, et al.
Applied Physics Letters