P. Pleshko, N. Apperley, et al.
Displays
Paper
An Investigation of the Potential of MOS Transistor Memories
Abstract
The design and performance characteristics of a 128X64 MOS transistor memory is given. The storage cell used operates with a low standby power, 0.1 mW. The memory operates with a 12-ns access time, 35-ns read cycle time, and a 60-ns write cycle time. Copyright © 1966 by The Institute of Electrical and Electronics Engineers, Inc.
Related
L.G. Heller, L.M. Terman
IEEE JSSC
Christophe R. Tretz, C.T. Chuang, et al.
IEEE International SOI Conference 1998
Conference paper
Limits - some are more fundamental than others
L.M. Terman
ICSICT 1995