A 1 mv MOS comparator
Y.S. Yee, L.G. Heller, et al.
ESSCIRC 1977
A two-stage weighted capacitor network for A/D and D/A conversion utilizing a feedback amplifier is described. The two-stage weighted capacitor DAC requires a smaller range of capacitor values than the conventional weighted capacitor DAC and is not subject to the nonlinear effects of parasitic capacitance. Experimental results of such a DAC implemented using a conventional n-channel metal-gate MOS process are presented. A discussion of the comparative accuracy and area of one-and two-stage weighted capacitor DAC's on the basis of capacitor tracking is given. Copyright © 1979 by The Institute of Electrical and Electronics Engineers, Inc.
Y.S. Yee, L.G. Heller, et al.
ESSCIRC 1977
L.M. Terman
IEEE Transactions on Magnetics
L.M. Terman
ICSICT 1995
L.M. Terman
ISSCC 1978