Scaling Millimeter-Wave Phased Arrays: Challenges and Solutions
Alberto Valdes-Garcia, Bodhisatwa Sadhu, et al.
BCICTS 2018
An integral-path self-calibration scheme is introduced as part of a 20.1 GHz to 26.7 GHz low-noise PLL in 32 nm CMOS SOI. A dual-loop architecture in combination with an integral path measurement and correction scheme desensitizes the loop transfer function to the VCO's small signal gain variations. The spread of gain peaking is reduced by self-calibration from 2.4 dB to 1 dB, when measured at 70 sites on a 300 mm wafer. The PLL has a measured phase noise @10 MHz offset of-126.5 dBc/Hz at 20.1 GHz and-124.2 dBc/Hz at 24 GHz © 2012 IEEE.
Alberto Valdes-Garcia, Bodhisatwa Sadhu, et al.
BCICTS 2018
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VLSI Circuits 2013
Asaf Tzadok, Alberto Valdes-Garcia, et al.
IMS 2020
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