Process-variation-tolerant zero skew clock routing
Shen Lin, C.K. Wong
Annual ASIC Conference and Exhibit 1993
A popular algorithm to compact VLSI symbolic layout is to use a graph algorithm similar to finding the “longest path” in a network. The algorithm assumes that the spacing constraints on the mask elements are of the lower bound type. However, to enable the user to have close control over the compaction result, a desired symbolic layout system should allow the user to add either the equality or the upper bound constraints on selected pairs of mask elements as well. This paper proposes an algorithm which uses a graph-theoretic approach to solve efficiently the compaction problem with mixed constraints. © 1983 IEEE
Shen Lin, C.K. Wong
Annual ASIC Conference and Exhibit 1993
Y.F. Wu, P. Widmayer, et al.
Acta Informatica
Charles Chiang, Majid Sarrafzadeh, et al.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Shou-Hsuan Stephen Huang, C.K. Wong
BIT