An Algorithm for Synthesis of Multiple-Output Combinational Logic

A computer-oriented algorithm for synthesizing combinational logic circuits from a collection of functionally packaged circuits is developed. The algorithm uses a hierarchy of “goals” in iterative decision process in a manner similar to that employed by theorem proving and game playing programs. With each iteration a set of “tasks” finds the circuit package which satisfies the highest level goal while meeting circuit constraints. A programmed version of the synthesis algorithm for the IBM 1620 is described, and a sample circuit implementation is given. Copyright © 1968 by The Institute of Electrical and Electronics Engineers, Inc.