About cookies on this site Our websites require some cookies to function properly (required). In addition, other cookies may be used with your consent to analyze site usage, improve the user experience and for advertising. For more information, please review your options. By visiting our website, you agree to our processing of information as described in IBM’sprivacy statement. To provide a smooth navigation, your cookie preferences will be shared across the IBM web domains listed here.
Publication
IEEE Electron Device Letters
Paper
A Reduced-Field Design Concept for High-Performance Bipolar Transistors
Abstract
This paper describes a device profile design concept that reduces the junction field, and thus the high-field-induced leakage currents as well as the avalanche current. The insertion of an i-layer of thickness equal to the depletion-layer width of the original n + -p+ junction can lower the junction field by about a factor of 2. Computer studies show that using this design, the collector avalanche current can be reduced by more than one order, while compromising little in the switching speed of the transistor. © 1989 IEEE