Abstract
Most existing buffering aigorithms neglect the impact of inductance on circuit performance, which causes large error in circuit analysis and optimization. Even for the approaches considering inductance effects, their delay models are too simplistic to catch the actual performance. As delay-length dependence is approaching linear with inductance effect [1], fewer buffers are needed to reduce RLC delay. This motivates this work to propose a new algorithm for RLC buffer insertion. In this paper, a new buffer insertion algorithm considering inductance for intermediate and global interconnect is proposed, based on downstream impedance instead of traditional downstream capacitance. A new pruning technique that provides tremendous speedup and a, new frequency estimation method that is very accurate in delay computation are also proposed. Experiments on industrial netlists demonstrate that our new algorithm reduces the number of buffers up to 34.4% over the traditional van Ginneken's algorithm that ignores inductance. Our impedance delay estimation is very accurate compared to SPICE simulations, with only 10% error while the delay model used in the previous RLC algorithm has 20% error [2]. The accurate delay model not only reduces the number of buffers, but also brings high fidelity to the buffer solutions. Incorporating slew constraints, the algorithm is accelerated by about 4x with only slight degradation in solution quality. Copyright 2006 ACM.