A mask reuse methodology for reducing system-on-a-chip cost

Abstract

Today's system-on-a-chip (SoC) design methodology provides an efficient way to develop highly integrated systems on a single chip by utilizing pre-designed intellectual property (IP) or cores. However, once assembled, the physical design and manufacturing process that follows does not benefit from the reuse of these cores. We propose an alternative mask reuse methodology (MRM) where most cores are provided with hardened layouts, significantly reducing the number of components for chip-level processing and the associated turn-around time. In addition, each core has a pre-verified mask set, which can be re-used to significantly reduce the overall mask cost and mask manufacturing time. Since mask cost and design and verification times are rapidly becoming prohibitive for low or even medium volume ASIC parts, the proposed MRM methodology can help reduce the barrier for ASIC parts. We provide details of the methodology, as well as an assessment of its impact on design time and design cost with an example of a network processor SoC. © 2005 IEEE.