A generalized algorithm for CMOS circuit delay, power, and area optimization

Abstract

A generalized algorithm for CMOS driver inverter chain optimization is described. In this optimization algorithm, the inverter circuit model is refined by including not only all the involved currents, but also takes into account high field mobility degradation. The calculated delay times agree very well with ASTAP simulations for a wide range of capacitances and input slew rates. The power-delay product and the area factor are also calculated in the circuit delay optimization procedure. Inclusion of these two factors allows interactive optimization for the number of stages and the transistor sizes of the circuits. © 1988.