A comprehensive evaluation of major phase shift mask technologies for isolated gate sinictuies in logic designs

Abstract

This paper presents a comparative analysis ofbinary 'chrome-on-glass', attenuated, biased rim, and phase edge shifted DUV lithography solutions for advanced circuitry in the sub-250nm image size regime. Lithography techniques are compared based on design complexity, ground rule impact, process latitude, and cost. Process latitude is compared over a feature size range of200nm-500nm based on DOF versus image size calculations for a common exposure dose as well as calculations of image size linearity as determined by relative print biases over the feature size range of interest. Data are presented from aerial image simulations (SPLAT1), aerial image measurements (AIMS®2), and SEM measurements. Phase edge shifted designs clearly exhibit the largest process window for 200nm line widths exposed on a O.5NA 248nm DUV stepper. Initial studies on phase edge design ground rules also indicate that it is possible to provide circuit designers with rules that will allow the addition of phase shift and trim designs with less than 10% impact on layout density in well designed layouts.3 The complexity ofthe mask engineering (design as well as manufacture) and exposure process for this 'hard' phase shifting technique warrants the study of less powerful but also less restrictive phase shifting options. This paper investigates the tradeoffs associated with various applicable phase shift mask (PSM) techniques and presents recommendations based on specific program requirements.