High-speed split-emitter I2L/MTL memory cell
Siegfried K. Wiedmann, Denny D. Tang
ISSCC 1981
This paper describes a circuit concept for reducing the soft error of highspeed flip-flop-type memory cells. For bipolar static memory cells, the essence of the concept is that the potential at the common-emitter node of the cross-coupled transistors (flip-flop) should be allowed to swing freely. This can be implemented by decoupling the common-emitter node from the heavily capacitively loaded lower word line, for example, by inserting a current source or a current mirror betweeen the two. The predicted improvement of QCRIT, soft-error rate, and the experimental results are presented. © 1988 IEEE
Siegfried K. Wiedmann, Denny D. Tang
ISSCC 1981
Tak H. Ning, Denny D. Tang
Proceedings of the IEEE
Ching-Te Chuang, Denny D. Tang, et al.
IEEE Journal of Solid-State Circuits
Tak H. Ning, Denny D. Tang
IEEE T-ED