A 2.2 W, 80 MHz Superscalar RISC Microprocessor

Abstract

A 28 mW/MHz at 80 MHz structured-custom RISC microprocessor design is described [1], This 32-b implementation of the PowerPC™ architecture is fabricated in a 3.3 V, 0.5 μm, 4-level metal CMOS technology, resulting in 1.6 million transistors in a 7.4 mm by 11.5 mm chip size. Dual 8-kilobyte instruction and data caches coupled to a high performance 32/64-b system bus and separate execution units (float, integer, load-store, and system units) result in peak instruction rates of three instructions per clock cycle. Low-power design techniques are used throughout the entire design, including dynamically powered down execution units. Typical power dissipation is kept under 2.2 W at 80 MHz. Three distinct levels of software—programmable, static, low-power operation—for system power management are offered, resulting in standby power dissipation from 2 mW to 350 mW. CPU to Bus clock ratios of 1×, 2×, 3×, and 4× are implemented to allow control of system power while maintaining processor performance. As a result, workstation-level performance is packed into a low-power, low-cost design ideal for notebooks and desktop computers. © 1994 IEEE