A 22-ns 1-Mbit CMOS High-Speed DRAM with Address Multiplexing

Abstract

This paper describes a I-Mbit high-speed DRAM (HSDRAM), which has a nominal random access time of less than 27 ns and a column access time of 12 ns with address multiplexing. A doublepolysilicon double-metal CMOS technology having PMOS arrays inside n-wells was developed with an average 1.3-μm feature size. The chip has also been fabricated in a 0.9 X shrunken version with an area of 67 mm², showing a 22-ns access time. The chip power consumption is lower than 500 mW at 60-ns cycle time. This HSDRAM, which provides SRAM-like speed while retaining DRAM-like density, allows DRAM’s to be used in a broad new range of applications. © 1989 IEEE