A 12nm Agile-Designed SoC for Swarm-Based Perception with Heterogeneous IP Blocks, a Reconfigurable Memory Hierarchy, and an 800MHz Multi-Plane NoC

Abstract

This paper presents an agile-designed domain-specific SoC in 12nm CMOS for the emerging application domain of swarm-based perception. Featuring a heterogeneous tile-based architecture, the SoC was designed with an agile methodology using open-source processors and accelerators, interconnected by a multi-plane NoC. A reconfigurable memory hierarchy and a CS-GALS clocking scheme allow the SoC to run at a variety of performance/power operating points. Compared to a high-end FPGA, the presented SoC achieves 7 × performance and 62× efficiency gains for the target application domain.