A 400-ns-Settling-Time Hybrid Dynamic Voltage Frequency Scaling Architecture and Its Application in a 22-Core Network-on-Chip SoC in 12-nm FinFET Technology

Abstract

We have developed a dynamic-voltage-and-frequency-scaling (DVFS) architecture that combines a package-integrated buck voltage regulator (PIVR) with fully standard-cell-based digital low-dropout regulators (LDO) to support fine-grained control at the scale of individual accelerators with a settling time of 400ns. The PIVR has a power density of 309mW/mm2 and features full back-end integration of magnetic-core power inductors. During a workload study on a custom system on chip (SoC) consisting of four general-purpose RISC-V cores and 18 specialized accelerators, our hybrid voltage regulator (HVR) showed the highest power savings when compared with the other power management techniques (PMT) for workload durations above 1.1µs and a peak power savings of 23% over the baseline with no DVFS.