Lukas Kull, Danny Luu, et al.
ISSCC 2017
The increasing demand on bandwidth for communicating among processors through wired interconnects in large-scale servers motivates the increase in the lane-data-rate from the current 28Gb/s to 56Gb/s or further. Recently published works [1]-[3] demonstrated ADC-based receiver (RX) prototypes equalizing > 56 Gb/s PAM-4 symbols for legacy channels with pre-FEC BERs of less than 2E-4 satisfying IEEE p802.bj/bs pre-FEC BER requirements. While the ADC-based > 56 Gb/s PAM-4 RXs provide strong equalization performance using a large number of feed-forward equalization (FFE) taps and a few decision-feedback equalization (DFE) taps [1], [2] implemented in digital, their power consumption remains excessive due to heavy arithmetic operations in the DSP.
Lukas Kull, Danny Luu, et al.
ISSCC 2017
Alessandro Cevrero, Ilter Ozkaya, et al.
ISSCC 2019
Dan Corcos, Danny Elad, et al.
IRMMW-THz 2014
Toke M. Andersen, Florian Krismer, et al.
APEC 2013