Rapidus and IBM move closer to scaling out 2 nm chip production

Our world is powered by microchips. Nearly every device we own now houses chips, thanks to technical innovations that have shrunk the transistor node down to the nanometer scale. As demand grows for smaller and more performant chips that also require less energy, especially for AI applications, their architecture is changing, too. IBM is working on new and innovative ways to build these devices, overcoming the technical challenges that come with increasingly complex transistors and their shrinking footprints.

With this purpose in mind, scientists from IBM and Japanese chipmaker Rapidus have announced that they reached a critical milestone in consistently constructing chips with a 2-nanometer process. Using two different strategies for selective nanosheet layer reduction, they can now build IBM Research has been at the forefront of gate-all-around transistor technology for more than 15 years, and we’ve driven their evolution from single nanowires to stacked nanosheets. Nanosheets provide better electrostatic control than nanowires, while also making it possible to fit more transistors within a given footprint.nanosheet gate-all-around transistors with multiple threshold voltages (or multi-Vt), which allows for chips that can perform complex computations without requiring as much energy. The group found that they could do this without the metal gate boundary problems that tend to accompany this construction method. They present their new research today at the annual IEEE International Electron Devices Meeting (IEDM) in San Francisco.

Three years ago, IBM Research scientists showed off the world’s first 2 nanometer node chip, and two years ago, IBM and Rapidus formed a partnership to advance this technology to a place where it would be possible to fabricate 2 nm chips at scale. With their new results, the collaboration has brought this effort a crucial step closer to the goal of producing these chips before the end of this decade.

Kazuyuki Tomida, the general manager at Rapidus US, LLC, also mentioned, "Multi-Vt technology is a critical component of our nanosheet architecture. The joint publication of this technology research paper with IBM Research at the IEDM conference represents a substantial milestone for Rapidus. This achievement reinforces our confidence in realizing our goal of manufacturing in Hokkaido at our advanced IIM foundry."

New problems, new solutions

Producing 2 nm node chips isn’t just a matter of scaling components down, explained Dechao Guo, the director of advanced logic technology at IBM Research. It also introduces unique challenges compared to the previous industry standard, FinFET transistors. "To achieve our goals for 2 nm technology, we need process solutions with nanosheet gate-all-around architecture for multiple threshold voltages, which enable ultra-low threshold voltages for high-performance computing, and higher threshold voltages for low-power computing," he said.

Back in 2017, IBM scientists published a paper asserting that nanosheets would enable the industry to move beyond FinFET, to build even smaller and more efficient transistors. With this construction method, nanosheets completely surround the transistor gate with thin silicon sheets, making it possible to pack more transistors into a given space. But it also brought new challenges. The team has now demonstrated a vital step toward the first iteration of the next generation of microchips.

"Nanosheet is a very different structure compared to the previous generation FinFET, and it can be more complicated" said Ruqiang Bao, senior technical staff member at IBM Research. "The new production process we propose is simpler than the approach used previously, and we’re confident it will make it easier for our partner Rapidus to reliably make chips with 2 nm nanosheet technology at scale."

Healthy boundaries

"Multi-Vt presents multiple challenges when using nanosheet technology, so we’ve been solving them, one by one," said Bao. Over the years, they’ve had several achievements. The first two solutions they presented at IEDM in 2019: Tsus pinchoff and volumeless multi-Vt. These solve the issues raised by This is sheet-to-sheet spacing, or Tsus, the space between any two nanosheets.Tsus for replacement metal gate patterning of materials onto chips. "The material required for multi-Vt is less than 1 nm thick, and the material diffuses into the underlying structure, hence making it essentially volumeless," said Guo.

In 2020, the team unveiled dual-dipole integration, which provided the solution to further reduce the threshold voltage for both types of semiconductor channels, which are called n-type and p-type and have differing electrical properties. This approach broke threshold voltage limitations, which enhanced individual transistor performance and improved the flexibility of volumeless multi-Vt. At IEDM in 2023, Bao and his colleagues demonstrated an application that dual-dipole integration makes possible: a transistor that’s well suited for liquid nitrogen cooling, something that can improve device performance but which most existing transistors aren’t built to handle.

An issue they addressed in this new paper was that the high transistor density of 2 nm nanosheet technology means there is a tight N-P space, which is the distance between n-type and p-type semiconductor channels. Within this narrow space, a thin layer patterning of materials selectively enables dipole materials for volumeless multi-Vt, acting as a sacrificial layer or active work function metal for multi-Vt. This strategy is necessary to integrate high-Vt devices, while a thick layer patterning defines low-Vt devices. Together, they form the full complement of multi-Vt devices in the transistors. The team used two selective layer reduction (SLR) approaches, which they named SLR1 and SLR2, to solve the problems that come along with these patterning techniques.

In one of the functional units on these chips, the N-P space can be less than 40 nm across, leaving less leeway to accommodate undercutting of the metal gate boundary when patterning such thin layers, which can create structural problems. At such a tiny scale, any imperfections can have drastic impacts on a semiconductor’s performance. Researchers have also observed that plasma ions used for etching the chips can damage gate dieletrics and inadvertently thicken interfacial layers, degrading device performance and reliability. A new etch process was developed to solve this issue. And then using SLR1, a thin layer (either thin sacrificial layer or thin active work function metal layer) addressed the problem of functional materials being undercut in the tiny space between these two transistors.

With SLR2, they addressed a similar type of undercutting that happened with the thick work function metal. In experiments, they demonstrated they could thin down the material only in the N-P space, while avoiding undercutting beneath the gate itself.

Together, these strategies strengthen nanosheet multi-Vt technology as the likely replacement for FinFET this decade, the researchers said.

"This innovation enables us to meet the exacting requirements of construction in nanosheet architecture, something that wasn’t possible with FinFET architecture," said Guo. "We aim to develop and qualify this multi-Vt production technology and transfer it to Rapidus for manufacturing."