Plasma Activated Low-temperature Die-level Direct Bonding with Advanced Wafer Dicing Technologies for 3D Heterogeneous Integration
- Katsuyuki Sakuma
- Dishit Parekh
- et al.
- 2021
- ECTC 2021
Publications
54 results for Chiplets
Copper Content Optimization for Warpage Minimization of Substrates with an Asymmetric Cross-Section by Genetic Algorithm
- Hiroyuki Mori
- Sayuri Kohara
- 2021
- ECTC 2021
3D Die-Stack on Substrate (3D-DSS) Packaging Technology and FEM Analysis for 55um-75um Mixed Pitch Interconnections on High Density Laminate
- Katsuyuki Sakuma
- Mukta Farooq
- et al.
- 2021
- ECTC 2021
Co-package technology platform for low-power and low-cost data centers
- Konstantinos Papatryfonos
- David R. Selviah
- et al.
- 2021
- Applied Sciences
3-D Die Stacking with 55 μm Pitch Interconnections on Advanced Ground-Rule Laminate for Artificial Intelligence System
- Katsuyuki Sakuma
- Mukta Farooq
- et al.
- 2021
- IEEE Transactions on CPMT
Packaging and Antenna Integration for Silicon-Based Millimeter-Wave Phased Arrays: 5G and Beyond
- Xiaoxiong Gu
- Duixian Liu
- et al.
- 2021
- IEEE Journal of Microwaves
Optical Communication and Energy Conversion for Small-Footprint Edge Computing
- Ning Li
- 2020
- MRS Spring/Fall Meeting 2020
Plating-free Bumping by Cu Nanopaste and Injection Molded Solder (IMS) for Fine Pitch Flip Chip Joining
- Toyohiro Aoki
- Eiji Nakamura
- et al.
- 2020
- ECTC 2020
Detection of Printable EUV Mask Absorber Defects and Defect Adders by Full Chip Optical Inspection of EUV Patterned Wafers
- Luciana Meli
- Ravi Bonam
- et al.
- 2017
- IEEE Trans Semicond Manuf
Proposal of Package Structure Requirements for Effective Cooling from the Bottom Side of Chips (from the Substrate Side), Aiming for a Three-Dimensional (3D) Chip Stack
- Keiji Matsumoto
- Hiroyuki Mori
- 2016
- ECTC 2016