Publications

2 results for Kenji Yanagisawa

A 500 MHz Random Cycle, 1.5 ns Latency, SOI Embedded DRAM Macro Featuring a Three-Transistor Micro Sense Amplifier
- - John Barth
  - William R. Reohr
  - et al.
- 2008
- IEEE Journal of Solid-State Circuits
A 500MHz random cycle 1.5ns-latency, SOI embedded DRAM macro featuring a 3T micro sense amplifier
- - John Barth
  - William Reohr
  - et al.
- 2007
- ISSCC 2007