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Publication
IEDM 2007
Conference paper
Write strategies for 2 and 4-bit multi-level phase-change memory
Abstract
We discuss novel multi-level write algorithms for phase change memory which produce highly optimized resistance distributions in a minimum number of program cycles. Using a novel integration scheme, a test array at 4bits/cell and a 32kb memory page at 2bits/cell are experimentally demonstrated. © 2007 IEEE.