Wafer level underfill for area array Cu pillar flip chip packaging of ultra low-k chips on organic substrates

Abstract

Wafer level underfill (WLUF), coated and B-staged on the wafer before dicing and flip chip bonding, protects and preserves interconnects and Back-End-of-Line (BEOL) structures by the presence of the underfill during the chip joining process. However, there are significant new challenges in formulating WLUF materials and developing the processes for area array flip chip packaging of silicon chips on organic substrates. The use of highly filled WLUF in conjunction with Ultra Low-k (ULK) chips which are larger than 10 x 10 mm and interconnected with Cu pillars to organic substrates has not yet been reported in the literature. It has been very challenging to achieve 100% electrically and metallurgically good Pb-free solder joints without WLUF voids. In this paper, details of flip chip packaging processes with highly filled WLUF materials (60 wt% fillers) will be presented including coating, dicing, bonding, and curing. The size of the test chip was 13x17mm and the test substrate was 42.5x42.5mm with over 8,000 area array interconnects. The chip bumps were 40 micron tall Cu pillars capped with 10 microns of SnAg solder (Ag > 1.5 wt%) and the pre-solder on the substrate was SnAgCu (Ag > 3.0 wt%). During the WLUF spin coating process, it is important to maintain uniform filler distribution as well as thickness uniformity. We achieved a tack-free surface after B-stage cure and the surface roughness was less than 0.2 micron. Since the wafer has ULK (k<2.4) dielectric, the wafer requires laser grooving before the blade dicing to reduce the stress during wafer sawing. We introduced a new dicing method to apply laser grooving for WLUF flip chip packages. When WLUF is used for flip chip packaging of 13x17 mm size chips on organic substrates, the WLUF should be inherently fluxing to achieve metallurgically good solder joints by melting and solidification of the solder during the bonding process because larger size area array chip packages require higher reliability criteria than smaller size peripheral chip packages. However, the flux capability is a likely source of voids in the WLUF after bonding. These voids were eliminated during a post cure process of the WLUF material by using hydrostatic pressure. In addition, fillers in the 60 wt% loaded WLUF must not be trapped in the solder joints, so the viscosity of the WLUF must remain low until the solder fully melts to make metallurgically good interconnections from the center to the corners of the chip. Cross sectional analysis was used to study the geometry of flip chip joints and filler distribution in the perimeter and the center of the chip. It was confirmed that solder joints were metallurgically good with no filler entrapment and that the filler was uniformly distributed. Non destructive X-ray images showed that there was no solder joint bridging in the entire chip area. C-SAM (C-Mode Scanning Acoustic Microscopy) confirmed that the integrity of the BEOL layer was preserved and that any WLUF voids that existed after bonding had been eliminated after full cure under hydrostatic pressure. © 2012 IEEE.