Verification scheme for pipelined vector architectures

Abstract

As a means for improving performance, advanced vector processors use an extension of pipelining, called vector chaining, whereby the execution of independent instructions is overlapped. The complexity of vector chaining architectures, together with their inherent parallelism and asynchrony, renders their verification extremely difficult. This paper presents an efficient simulation-based scheme for verifying such architectures. The scheme presented here can be applied to other verification problems where the simulation expected results is not deterministic but belongs to set a of computable possibilities.