TSV/FET proximity study using dense addressable transistor arrays

Abstract

Addressable transistor arrays (∼20,000 devices) provide an attractive test vehicle to study TSV/FET proximity effects in a statistically meaningful way. FET/TSV proximity effect studies have been performed at the 45 nm node using a dense addressable parametric diagnostic (APD). We have found that a carefully designed TSV integration sequence at this node has minimal impact on the quality of devices. For the integration scheme studied, it was found that stress of the Si in the vicinity of the TSV had minimal impact on device characteristics for annular Cu TSVs, for devices placed as close as ∼3μm to the TSV.