Triple metal routing methodology for ASIC sea-of-cells design

Abstract

This paper presents a general sea-of-cells routing methodology for state-of-the-art ASIC design, where three layers of metal are available for signal interconnection. As routing channels are defined over the cells, this routing system not only deals with various blockages on different layers, but also considers performance constraints such as wire widths and coupling noises for mixed analog/digital ASIC design.