Thermo-Compression Bonding and Mass Reflow Assembly Processes of 3D Logic Die Stacks

Abstract

3D multi-layer chip stacking is a significant assembly challenge with dependencies on die size and thickness, interconnect pitch, bump diameter, number of dies involved, and die warpage. The assembly processes used to overcome the technical difficulties associated with the stacking of medium and large logic dies with fine pitch copper pillar bumps is discussed, including mass reflow and thermo-compression bonding on 3 and 4 layers chip stacks.