Arun Reddy Chada, Young H. Kwark, et al.
EPEPS 2009
What package improvements are required for dense, high aggregate bandwidth buses running at data rates beyond 10 Gb/s per pin, and when might optical interconnects on the board be required? We present a study of distance and speed limits for electrical on-board module-to-module links with an eye to answering these questions. Detailed electrical link models have been validated with active, high-speed differential bus measurements utilizing a 16-channel link chip with programmable equalization and a per-channel data rate of up to 11 Gb/s. Electrical signalling limits were then determined by extrapolating our models to higher speeds, and these limits were compared to the results of work on on-board optical interconnects. © 2008 IEEE.
Arun Reddy Chada, Young H. Kwark, et al.
EPEPS 2009
Ki Jin Han, Mark B. Ritter, et al.
EPEPS 2010
Young H. Kwark, Miroslav Kotzev, et al.
IMS 2011
Dipankar Raychaudhuri, Ivan Seskar, et al.
MobiCom 2020