The effective drive current in CMOS inverters

Abstract

A simple but accurate expression for the effective drive current, Ieff, for CMOS inverter delay is obtained. We show that the choice Ieff = (IH + IL)/2, where IL=Ids(Vgs=Vdd/2, Vds=Vdd), and IH=Ids(Vgs=Vdd, Vds=Vdd /2) is defined, accurately predicts inverter delay when tested against compact models over a variety of conditions and against hardware results in 90 nm node technology. Furthermore this definition of Ieff accurately captures the delay behavior of non-traditionally scaled devices, where mobility and VT/ Vdd are scaled in neither a regular nor uniform manner.