Indranil R. Bardhan, Sugato Bagchi, et al.
JMIS
The IBM POWER4 processor is a 174-million-transistor chip that runs at a clock frequency of greater than 1.3 GHz. It contains two microprocessor cores, high-speed buses, and an on-chip memory subsystem. The complexity and size of POWER4, together with its high operating frequency, presented a number of significant challenges for its multisite design team. This paper describes the circuit and physical design of POWER4 and gives results that were achieved. Emphasis is placed on aspects of the design methodology, clock distribution, circuits, power, integration, and timing that enabled the design team to meet the project goals and to complete the design on schedule.
Indranil R. Bardhan, Sugato Bagchi, et al.
JMIS
Erich P. Stuntebeck, John S. Davis II, et al.
HotMobile 2008
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SPIE Advances in Semiconductors and Superconductors 1990
Renu Tewari, Richard P. King, et al.
IS&T/SPIE Electronic Imaging 1996