The architecture and analysis of a hybrid number system processor

Abstract

A hybrid number system processor is studied and analyzed. This processor uses the FLP (floating point) to LNS (logarithm number system) conversion algorithm to transform all the incoming 32-b floating-point numbers into 32-b logarithmic numbers. Arithmetic operations are performed in the LNS domain. The output FLP results are also obtained by using the LNS to FLP conversion algorithm. All the arithmetic operations including addition and subtraction can be implemented by using the anti-logarithm PLA (programmable logic array). Error analysis indicates that the Taylor series truncation leads to very small error when the ROM size is properly chosen for the desired precision. Consequently, the finite width truncation becomes the major source of conversion errors.