Terabit/s packaging design for testing of high-speed IC transceivers

Abstract

An electrical packaging platform to support the testing of high-speed IC transceivers with aggregate data rates up to 0.48 Tb/s Tx + 0.48 Tb/s Rx (24 transmitters and 24 receivers up to 20 Gb/s per channel) is presented. The design requirements, potential solutions, and considerations for a successful implementation are discussed together with the characterization and evaluation of a passive interconnect system that spans package, board, and high-speed connectors. This platform is used to demonstrate the operation of VCSEL-based optoelectronic buses for short-reach applications relying on a custom IBM CMOS "holey" optochip.