Publication
IEEE ITC 1989
Conference paper

Synthesis of pseudo-random pattern testable designs

Abstract

A method of synthesizing scan designs that are testable with pseudorandom patterns is presented. The logic is first simplified by various transformations in a logic synthesis system. A fault simulator is then used to guide the placement of control points and observation points. In order to reduce the overhead, control points are shared when possible and a condensation network is used with the observation points. Experimental results which indicate that pseudorandom testability can be achieved with small area overheads using simple techniques are presented.

Date

Publication

IEEE ITC 1989

Authors

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