Brian Flachs, Shigehiro Asano, et al.
IBM J. Res. Dev
Paper
Synergistic processing in cell's multicore architecture
Abstract
Eight synergistic processor units enable the Cell Broadband Engine's breakthrough performance. The SPU architecture implements a novel, pervasively data-parallel architecture combining scalar and SIMD processing on a wide data path. A large number of SPUs per chip provide high thread-level parallelism. © 2006 IEEE.
Related
Steven C. Chan, Phillip J. Restle, et al.
IEEE Journal of Solid-State Circuits
Conference paper
Optimizing compiler for a CELL processor
Alexandre E. Eichenberger, Kathryn O'Brien, et al.
PACT 2005
H. Peter Hofstee, Sang H. Dhong, et al.
IEEE Micro