About cookies on this site Our websites require some cookies to function properly (required). In addition, other cookies may be used with your consent to analyze site usage, improve the user experience and for advertising. For more information, please review your options. By visiting our website, you agree to our processing of information as described in IBM’sprivacy statement. To provide a smooth navigation, your cookie preferences will be shared across the IBM web domains listed here.
Publication
IEEE Electron Device Letters
Paper
Sub-300-ps CBL Circuits
Abstract
This paper describes advanced charge-buffered-logic (CBL) circuits featuring double-poly self-alignment, a “free” epi-base lateral p-n-p (cutoff frequency = 300 MHz only), and deep trench isolation. Using 1.2-μm design rules and a modified push-pull output stage, a gate delay (fan-in = 3) of 278 ps was obtained at a dc current of 30 μA/gate. © 1989 IEEE